The Tru-SiPh™ Platform advantages stem from five major characteristics. Together, these provide a truly scalable photonic integration platform that can address multiple applications and markets.

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Our Fab

Our devices are fabricated in highly proprietary processes in our Temecula California silicon microstructures foundry. This fab has a 34-year history of providing unique solutions to the silicon and CMOS industry and continues to do so to this day. Using CMOS process tools and unique processes, the Tru-SiPh™ platform is fabricated, tested, and burned-in with a wafer scale process that radically changes the economics of high-performance optics. Our fab also supports integration structures for 2.5D and 3D packaging, useful for higher level integration and copackaged optics. In addition, Skorpios has its own high-volume tools for production of III-V epitaxy.

Proprietary process

Unlike merchant silicon processes squeezed into traditional CMOS fabs, our process for true heterogeneous integration is protected by over 125 worldwide patents (with 25 more pending), and easily twice that number of trade secrets in our own fab. Custom tools have been developed to facilitate our unique process to scale to any reasonable volume.

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Platform

Our thick silicon approach, not available in commercial foundries, provides optics which are inherently insensitive to polarization, provide higher optical confinement and tighter integration with lower losses. Size is further reduced by the integration of lasers and other elements in-plane with the silicon waveguides (rather than glued on top or fiber coupled in separately) and with waveguide fabrication occurring simultaneously on both material systems, no optical alignments are required and extensive reuse of III-V materials within a circuit is possible.

Integration

The tight waveguide confinement and embedded epitaxies allow for very high levels of integration in compact form factors for high yield and low cost. The architecture allows each epitaxy to be used for multiple purposes, without additional cost. For instance, SOAs can be simply implemented with lithography on the same piece of epitaxy as the laser.

Integration
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Wafer scale test and burn-in

Because lasers are incorporated in our structures along with all other optical elements, the photonic circuits can be self-tested. Internal lasers can be monitored with EA modulators or built-in photodiodes. Receivers can be tested with integrated lasers. The entire wafer is tested AND burned-in before die singulation and delivery to the customer, truly a wafer scale process end to end. Built in Self Test (BIST) is a feature of Tru-SiPh™.

Technology Comparison

Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • Good for One λ per Wafer
  • Hard to Integrate Lasers & SOAs with Different Wavelengths
  • Typical: Attach Fabricated Lasers Bulky, Low Density, No SOA
  • Low Thermal Impedance, Small Area
  • Multiple Lasers/SOAs on Each III-V EPI
  • Integrate Multi-λ Lasers per Chip
Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • Good for One λ per Wafer
  • Hard to Integrate Lasers & EAMs with Different Wavelengths
  • MZM: Bulky, Large Drive Voltage
  • Ring: Hard to Control, Nonlinear
  • Mini InP EAM, Small Drive Voltage
  • Good for Multi-λ per Chip
Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • External Mux/DeMux (PLC)
  • Integrated Mux, External DeMux
  • Integrated Tuning-Free Mux/DeMux
Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • High Loss
  • Large Layout
  • Low Loss
  • Compact Layout
  • Very Low Loss
  • Very Compact Layout
  • Insensitive to Fabrication Tolerances & Polarization
Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • Low-Level Integration
  • Co-Packaging of Discrete Devices
  • High-Level Integration
  • Some Optical Co-Packaging
  • Integrate All Devices on A Single Chip
  • No Optical Co-Packaging
Typical III-V Photonics Typical Si Photonics Skorpios Si Photonics
  • III-V Fab on 2”-3” Wafers
  • Low Yield, High Cost
  • CMOS Fab on 8”-12” Wafers
  • High Yield, Low Cost
  • CMOS Fab on 8”-12” Wafers
  • High Yield, Low Cost
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